NOC | Digital VLSI Testing

Course abstract

Testing is an integral part of the VLSI design cycle. With the advancement in IC technology, designs are becoming more and more complex, making their testing challenging. Testing occupies 60-80% time of the design process. A well structured method for testing needs to be followed to ensure high yield and proper detection of faulty chips after manufacturing. Design for testability (DFT) is a matured domain now, and thus needs to be followed by all the VLSI designers. In this context, the course attempts to expose the students and practitioners to the most recent, yet fundamental, VLSI test principles and DFT architectures in an effort to help them design better quality products that can be reliably manufactured in large quantity.

Course Instructor

Prof. Santanu Chattopadhyay

Santanu Chattopadhyay received his PhD from Indian Institute of Technology (IIT) Kharagpur in 1996. He is currently a Professor in the Department of Electronics and Electrical Communication Engineering, IIT Kharagpur. His research interests include Embedded Systems, System-on-Chip (SoC) and Network-on-Chip (NoC) Design and Test, Power- and Thermal-aware Testing of VLSI Circuits and Systems. He has published more than 150 papers in reputed international journals and conferences. He has published several text and reference books in the related areas. He is a senior member of IEEE and an editorial board member of IET Circuits Devices and Systems.
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